1. Field of the Invention
The present invention relates to a pulse counting device for counting a pulse signal generated in relation to a variation in a measurand such as the running speed or the number of engine r.p.m. of automobiles or motorcycles.
2. Description of the Prior Art
There are generally known devices for displaying a measurand based on pulses produced in proportion to the measurand. The known devices operate by counting the pulses proportional to the measurand with a gate time preset by a reference clock signal, latching the count, and successively updating and displaying the count. In the prior devices, a time in which the count can be updated is determined by setting the gate time preset by the reference clock signal, and the measurement accuracy is governed by the density of pulses applied as an input within the gate time. Generally, however, a higher density of pulses proportional to variations in the measurand requires a considerably more expensive pulse generator. Even if the pulse generator is provided inexpensively, the number of pulses generated in a clock period when the automobile or motorcycle is running at high speed, require a counter capacity to be increased, with the result that the device is quite large in overall size and expensive. It would easily be possible to increase the gate time to relatively increase the number of pulses applied in the gate time. However, this method would fail to follow a rapid change in the measurand.
One general arrangement is shown in FIG. 1 of the accompanying drawings. As shown in FIG. 1, when pulses proportional to a variation in a measurand are applied to an input terminal 1, the pulses are counted by a counter 2 connected to the input terminal 1 and having a counting period. When the counting operation of the counter 2 is completed, counts from the counter 2 are stored in a plurality of, e.g., four registers 3a, 3b, 3c, 3d, and the counts stored in the registers 3a . . . 3d are added by an adder 4 which produces a sum P. A value dependent on the sum P is then displayed on a display 5.
Operation of the circuit arrangement illustrated in FIG. 1 will be described with reference to FIG. 2. When pulses proportional to a variation in a measurand such as a running speed are applied from the input terminal 1, pulse numbers P1, P2, P3, P4 counted periodically at times in which the display in a display unit 5 is switched to display a new value which may be 1 second for example, are stored respectively in the registers 3d, 3c, 3b, 3a at times t1, t2, t3, t4 when the counter 2 finishes pulse counting. The stored pulse numbers P1, P2, P3, P4 are added by the adder 4, and a running speed dependent on the sum (P1+P2+P3+P4) is displayed on display unit 5.
If the running speed is abruptly reduced to 0 km/h at t4, then a pulse number P5=0 counted in a new display switching time t4-t5 is newly applied to the counter 3a at a count completing time t5, and the pulse numbers P4, P3, P2 stored in the registers 3a, 3b, 3c are successively shifted into the registers 3b, 3c, 3d, respectively. The pulse number P1 counted in the oldest display switching time t0-t1 is shifted out of the registers. A running speed dependent on the sum (P2+P3+P4+0) given by the adder 4 is displayed on the display unit 5. Therefore, the display still indicates a certain speed value notwithstanding the running speed is 0 km/h in reality.
At a next count completing time t6, a pulse number P6=0 counted in a new display switching time t5-t6 is newly entered into the register 3a, and the pulse numbers P5, P4, P3 stored in the registers 3a, 3b, 3c are successively shifted into the registers 3b, 3c, 3d respectively. The pulse number P2 counted in the oldest display switching time t1-t2 is shifted out of the registers. A running speed dependent on the sum (P3+P4+0+0) given by the adder 4 is displayed on the display unit 5. Therefore, the display still indicates a certain speed value notwithstanding the running speed is 0 km/h in reality.
At a next count completing time t7, the pulse numbers P3 through P6 stored in the registers 3a through 3b are shifted, and the pulse number P3 counted in the oldest display switching time t2-t3 is shifted out of the registers. A pulse number P7=0 counted in a new display switching time t6-t7 is newly entered into the register 3a. A running speed dependent on the sum (P3+0+0+0) given by the adder 4 is displayed on the display unit 5, the displayed value being not yet 0 km/h.
At a count completing time t8, the pulse numbers P4 through P7 stored in the registers 3a through 3d are shifted, and the pulse number P4 counted in the oldest display switching time t3-t4 is shifted out of the registers. A pulse number P8=0 counted in a new display switching time t7-t8 is newly entered into the register 3a, whereupon the sum of the registers 3a through 3d becomes (0+0+0+0) and the running speed as displayed on the display unit 5 is 0 km/h.
With a speedometer employing the above conventional pulse counting device, four counting times (or four seconds in the example) are required before the displayed value actually indicates 0 km/h after the motor vehicle has stopped. The speedometer is therefore disadvantageous in that its response is slow and the displayed speed value is different from an actual speed felt by the driver.